As compared with an amorphous silicon thin film transistor (a-Si TFT), a low temperature poly-silicon thin film transistor (LTPS TFT) has several advantages, such as a very high mobility up to about 10-100 cm2/Vs, capability of fabricating at relatively low temperature (e.g., lower than 600° C.), flexible choice in the substrate, low production cost. These features of LTPS TFTs are remarkable advantages for fabricating a flexible display, and have made LTPS TFTs to become the most important device for the industrial production of a flexible display.
Currently, one of the issues for LTPS TFTs is the ohmic contact between the source and drain and the active layer of poly silicon is not satisfactory. In particular, in a top gate TFT, after the active layer, a gate insulating layer, and a gate are formed on the substrate, through holes are formed in the source-and-drain-to-be-formed regions of the active layer and the gate insulating layer, so as to form a pattern of gate and source. However, the poly silicon layer is prone to be pierced during forming the through holes, which leads to an ohmic contact with a small area and large contact resistance. This phenomenon is more detrimental during fabricating the flexible device. In addition, the annealing temperature is relatively low for the flexible device. The ohmic contact is originally not satisfactory. In case the poly silicon is pierced, the contact resistance will further increase, and the device will suffer from serious degradation in characteristics.
Therefore, there is a desire to improve contact between the source and drain and the active layer in the art.